CSLLSRAM090_4KX40 & CSLLSRAM090_8KX40 90NM LOW LEAKAGE STATIC RANDOM ACCESS MEMORIES
The CSLLSRAM090 is a x40 single port SRAM in either 4Kword or 8Kword configurations that is designed into TSMC’s CLN90LP CMOS process. It uses the lower four metals (all thin) and can be freely over-routed with higher level interconnects.
The design is optimized for standby power and makes use of both standard Vt and high Vt MOSFETs. A deep sleep mode is embodied which shuts down the power to all
peripheral circuitry and to selected banks of SRAM cells. In those banks where data is to be retained, the internal power supply connection is maintained and an n-channel source biasing technique is used to reduce leakage current when not being accessed.
The design uses conventional row-column physical decoding and partitions the array vertically into four (4KWord) or eight (8KWord) banks. A segmented bitline
architecture with local column decode is used to improve speed and reduce active power consumption.
A synchronous clear function is implemented for the addressed bank, where 128 address locations are cleared
to zero in one clock cycle.