Custom Memory

//Custom Memory
Custom Memory 2017-08-28T18:40:23+00:00

CSLLSRAM180 8KX32 0.18ΜM LOW LEAKAGE STATIC RANDOM ACCESS MEMORY

The CSLLSRAM180 is an 8Kx32 single port static RAM that is designed into TSMC’s 0.18μm CMOS process. It uses the lower four metals (all thin) and can be freely overrouted with higher level interconnects.

The design is optimized for standby power and makes use of standard Vt and high Vt thin oxide MOSFETs plus thick oxide (3.3V) I/O transistors. A deep sleep mode is embodied which shuts down the power to all peripheral circuitry and to selected banks of SRAM cells. In those banks where data is to be retained, the internal power supply connection is maintained and an n-channel source biasing technique is used to reduce leakage current when not being accessed.

The design uses conventional row-column physical decoding and partitions the array vertically into eight banks. A segmented bitline architecture with local column decode
is used to improve speed and reduce active power consumption.

 

MEMORY COMPILER FEATURES

  • BIST (Built-In Self Test) Aware
  • Customer may use internal test muxes or external BIST
  • Area or Performance Switch
  • Customer sets compiler priority switch to compile for optimal speed or size
  • Byte Masking
  • Subword select option
  • Port A/B setup mode (Read/Write) option (for DP SRAM)
  • Security and Test Mode for OTP NVM
  • Selectable Charge Pump Option for OTP NVM Cell Programming
  • Built in internal VPPI source, or
  • External source

MEMORY COMPILER CHARACTERISTICS

Data Access: Configurable

Dual Port: Each Port is configurable

Input Latching: Input signals are latched at rising clock edge

BIST: Configurable On/Off

Over Routing: Max 3 metal layers used

CSLLSRAM090_4KX40 & CSLLSRAM090_8KX40 90NM LOW LEAKAGE STATIC RANDOM ACCESS MEMORIES

The CSLLSRAM090 is a x40 single port SRAM in either 4Kword or 8Kword configurations that is designed into TSMC’s CLN90LP CMOS process. It uses the lower four metals (all thin) and can be freely over-routed with higher level interconnects.

The design is optimized for standby power and makes use of both standard Vt and high Vt MOSFETs. A deep sleep mode is embodied which shuts down the power to all
peripheral circuitry and to selected banks of SRAM cells. In those banks where data is to be retained, the internal power supply connection is maintained and an n-channel source biasing technique is used to reduce leakage current when not being accessed.

The design uses conventional row-column physical decoding and partitions the array vertically into four (4KWord) or eight (8KWord) banks. A segmented bitline
architecture with local column decode is used to improve speed and reduce active power consumption.

A synchronous clear function is implemented for the addressed bank, where 128 address locations are cleared
to zero in one clock cycle.

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